This invention relates generally to a process for fabricating a semiconductor device having an oxide-nitride-oxide layer and, more particularly, to a process for removing a portion of the oxide-nitride-oxide layer using an isotropic etch.
Semiconductor devices are currently in widespread use in a variety of electronic devices, such as computers, stereos, telephones, cameras, engine control units, and the like. Semiconductor devices include, but are not limited to, central processing units, non-volatile memory devices, and digital signal processors. One type of semiconductor device, non-volatile memory devices, are currently in use in electronic devices that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells within these memory device can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of large blocks of memory cells using a single electrical current pulse.
Product development efforts in non-volatile memory device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode. Recently, development efforts have focused on dielectric materials for fabrication of the floating-gate electrode.
One important dielectric material for the fabrication of a flash EEPROM device is an oxide-nitride-oxide (ONO) layer. The ONO layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The ONO layer may serve as either a charge storage layer or an insulating layer in the flash EEPROM device. In one example, the ONO layer serves as a charge storage layer. During programming, electrical charge is transferred from the substrate to the nitride layer in the ONO layer. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the first oxide layer and become trapped in the nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the nitride layer near the source region. Because the nitride layer is not electrically conductive, the charge introduced into the nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in regions within a single continuous nitride layer. In one example, the ONO layer serves as an insulating layer for a floating gate structure within a flash EEPROM device.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory devices that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
In addition to non-volatile memory, such as a flash EEPROM, other semiconductor devices may include ONO layers as well. ONO layers can serve many different purposes, such as, for example an insulator or as a charge storage layer in a semiconductor device. While the recent advances in semiconductor fabrication technology have enabled semiconductor device designers to create much smaller semiconductor devices, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating an ONO layer within a semiconductor device presents several challenges. As the size of features within semiconductor devices has decreased, so has the thickness of the ONO layers. Selective removal of a thin ONO layer, that is an ONO layer of less than 1000 angstroms in thickness, has becomes increasingly difficult with conventional etching techniques, such as anisotropic etching.
As illustrated in FIG. 12, anisotropic etching requires the use of an anisotropic etch chamber 60. A semiconductor device 18 is placed upon a negative plate 66 within the anisotropic etch chamber 60 between a positive plate 64 and the negative plate 66. The negative plate 66 is grounded. An RF voltage V+ is applied to the positive plate 64 to excite gases within the anisotropic etch chamber 60 and convert the gases into high energy plasma 62. Because the semiconductor device 18 is placed on the negative plate 66, the semiconductor device 18 experiences a DC bias voltage of V+, which is typically in the range of 100 to 1000 volts. The high energy plasma 62, created by the DC bias voltage of V+ is accelerated from the positive plate 64 to the negative plate 66 and into the semiconductor device 18 at a relatively high rate of speed. Anisotropic etching can typically penetrate as much as 100 angstroms or more into the semiconductor device, and in particular into an ONO layer within a semiconductor device. If the ONO layer within a semiconductor device is thin, that is less than 1000 angstroms, anisotropic etching can cause damage to the semiconductor substrate beneath the ONO layer. Accordingly, advances in processes for fabricating a semiconductor device having an oxide-nitride-oxide layer and, more particularly, in processes for removing a portion of the oxide-nitride-oxide layer, are necessary.
According to a first aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.
According to another aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing a wet etch on the second oxide layer, wherein the wet etch is highly selective to oxides, and performing an isotropic etch on the nitride layer.
According to another aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing a first isotropic etch on the second oxide layer, and performing a second isotropic etch on the nitride layer.
According to another aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes performing an isotropic etch on the nitride layer.